In recent years, the data amount of images, especially moving images, has been increasing in order to satisfy high-definition and large-screen requirements. Therefore, technology that compresses and encodes moving picture data has been developed in view of the following cases or the like: where such moving picture data which has been increasing in amount is transmitted on a network, and where moving picture data is stored in a storage medium.
For example, there are international standards such as the MPEG-2 (Motion Picture Experts Group), the H264/MPEG-4AVC (Advanced Video Codec) and the like.
Moving picture data that has been encoded according to these standards is usually displayed while being decoded by an image decoding apparatus.
Although the current mainstream image size is 720 pixels 480 lines of standard TV (SDTV), it is expected that the use of an image size of 1920 pixels 1080 lines of high definition TV (HDTV), and the use of image size used in the digital cinema standard in which a screen size is larger will increase.
This digital cinema standard defines an image size of 2048 pixels 1080 lines which is called “the 2K standard”, and the image size of 4096 pixels 2160 lines which is called “the 4K standard”.
One-chip LSIs for decoding for these image sizes have been developed. However, when decoding is performed by one decoder, high-computing performance and a broad data bandwidth are needed as an image size becomes larger, causing high cost and high power consumption.
Technology has been proposed that realizes a high-performance decoding apparatus for HDTV by causing a plurality of decoders comparatively low in processing ability (e.g. decoders for SDTVs) to perform decoding processing in parallel (see Patent Document 1).
The following briefly describes the decoding apparatus using FIG. 18. Four image decoders (4, 5, 6, 7) which are decoders in each of which a bitstream transmitted from a transport decoder 1 is input (i) select, from bitstreams, slice data to perform decoding on, (ii) decode the selected slice data, and (iii) output the decoded slice data to frame memories (2, 3). Each of the image decoders (4, 5, 6, 7) selects a slice in a numerical order of slices, and starts decoding processing using the same frame memories simultaneously with a timing that each buffer reads data of the selected slice.
According to this technology, it is possible to realize high processing ability even if decoders comparatively low in processing ability are used.